I hope I have time to report my experience, in particular for HLS, with the new design tool
Archive for the ‘Vivado’ Category
Check out this clip for Vivado HLS 2012.2 in action:
Notice how easily it is to apply different HLS directives to the same C code to improve frame rate from 2fps to 81fps.
You can see the exploding potentials of FPGA in software engineers’ hands.
Xilinx announced Vivado today.
Looks like ISE goes up to version 13.4, and Vivado supports only 7-series FPGAs.
Here’s some more details from EDA 360 Xilinx Vivado Design Suite brings SoC design style to advanced-node FPGA development
I am told, Vivado will be available to the public on May 8th, two weeks away.
Xilinx makes ISE 14.1 available today (May 8).
Kind of confusing, names of ISE 14.1 (Rodin) vs Vivado.