Archive for April, 2012

Vivado – new Xilinx design tool

April 25, 2012

Xilinx announced Vivado today.
Looks like ISE goes up to version 13.4, and Vivado supports only 7-series FPGAs.

Here’s some more details from EDA 360 Xilinx Vivado Design Suite brings SoC design style to advanced-node FPGA development

I am told, Vivado will be available to the public on May 8th, two weeks away.

Update:
Xilinx makes ISE 14.1 available today (May 8).
Kind of confusing, names of ISE 14.1 (Rodin) vs Vivado.

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Zynq EPP

April 10, 2012

I went to annual Xilinx Technical Seminar today on Xilinx campus.

This year’s topic is all about Zynq. Here’s what I knew from the seminar.

ISE 14.1 will be out in about 2 weeks, it will bundle Rodin (currently in Beta 4). Rodin significantly reduces build time (ISE 13.2/13 hours vs Beta 2/5 hours), and memory used (16G vs 9G ) in the example for XC7V2000T device.

The video demo was performed on a ZC702 board. The FPGA hardware was built with AutoESL, the high-level synthesis tool, based on C code. The hardware accelerated edge detection is playable, and much smoother than software only edge detection.

Some Zynq boards, including ZED, are listed from Boards and Kits section from Xilinx website:

http://www.xilinx.com/products/boards_kits/zynq-7000.htm

I was told ZC702 should be available to order in summer.