Archive for the ‘HLS’ Category

Vivado is available

July 26, 2012

If you are a follower of XilinxInc, you may find
Vivado 2012.2, and ISE 14.2, are available today at Xilinx Downloads link.

I hope I have time to report my experience, in particular for HLS, with the new design tool

Vivado HLS in Action

May 18, 2012

Check out this clip for Vivado HLS 2012.2 in action:

Notice how easily it is to apply different HLS directives to the same C code to improve frame rate from 2fps to 81fps.
You can see the exploding potentials of FPGA in software engineers’ hands.

Vivado 2012.1

May 11, 2012

When I installed ISE 14.1 System Edition, I found Vivado 2012.1 comes with it.

I will contact Xilinx and Avnet FAEs to see if I could get early access license.

Vivado 2012.1

I’m told Vivado public access will be in July.

Vivado – new Xilinx design tool

April 25, 2012

Xilinx announced Vivado today.
Looks like ISE goes up to version 13.4, and Vivado supports only 7-series FPGAs.

Here’s some more details from EDA 360 Xilinx Vivado Design Suite brings SoC design style to advanced-node FPGA development

I am told, Vivado will be available to the public on May 8th, two weeks away.

Update:
Xilinx makes ISE 14.1 available today (May 8).
Kind of confusing, names of ISE 14.1 (Rodin) vs Vivado.