Run Linux on Avnet Spartan-6 LX9 MicroBoard

AV-LX9 MicroBoard is a new low cost Spartan-6 LX9 device based development kit from Avnet. XC6SLX9
has 1,430 slices, or 5,720 LUTs, and 32 Block RAM. Rich features, such as 64MB DDR, 128Mb SPI Flash, 10/100 Ethernet PHY, USB-UART port, JTAG, LEDs, DIP switches and expansion ports, make the board an affordable and very useful experimental prototyping tool.

Thanks for Avnet’s Frank for the LX9 MicroBoard, I was lucky to be able to try out the board early. My main goal was to get Petalinux running on this this USB-stick form factor board, with httpd server serving web pages and certain peripherals to demonstrate user defined functionalities. After many weekends’ efforts, I was always couple hundreds of LUTs in short to fit designs of MicroBlaze with MMU into LX9 device, even after removing most peripherals, and enabling Legalizer placement algorithm.

Then Petalogix’s John offered me a Linux BSP, used for hobby purpose. This convinced me the goal was possible, and kept me trying my own SOPC designs.

Finally I got it working before the recent Avnet LX9 MicroBoard SpeedWay Design Workshops. The keys were to remove non-essential MicroBlaze features and not use MDM’s JTAG-based UART thus saves a AXI4-Lite connection. I am sure it can go further to use less resources and/or add more peripherals, but still has a stable Linux running on the board.

Here’s how the working design was done in details. I am using PetaLinux SDK 2.1 and ISE 13.2 for 32 bit Linux, starting design flow from Project Navigator.

Create a new project based on Avnet LX9 MicroBoard XBD.

Create New ISE Project

Select Embedded Processor for Source Type with New Source Wizard.

Select Source Type

When BSB starts, choose AXI flow.

AXI Flow

And configure below processor, cache and peripherals.

Processor, Cache and Peripheral Configuration

Once XPS project is created, configure MicroBlaze by double clicking the IP from System Assembly View.

MicroBlaze with MMU Configuration

After select MMU configuration, click Advanced button to fine tune. The following setups can be done by going back and forth to enable then disable certain features. Here’s General configuration.

MicroBlaze General Configuration

Disable all exceptions.

MicroBlaze Exception Configuration

Make sure instruction cache base address is setup properly. This is the location where Linux kernel starts.

MicroBlase Cache Configuration

Here’s MMU setup.

MicroBlaze MMU Configuration

Enable MDM so XMD can be used to debug.

MicroBlase Debug Configuration

No need for Processor Version Registers.

MicroBlase PVR Configuration

Here’s the Interconnection I used.

MicroBlaze Interconnect Configuration

Buses setup is the last MicroBlaze configuration.

MicroBlaze Buses Configuration

Now configure MDM by disabling JTAG UART.

MDM Configuration

Here’s XPS System Assembly View when design is done.

XPS System Assembly View

Return to Project Navigator when XPS is closed. Add constraints by Project > Add Copy of Source.

ISE Add Constraints

Double click Generate Top HDL Source to create HDL instantiation template for the MicroBlaze design.

ISE Generate Top HDL Source

Export hardware design to SDK.

ISE Export Hardware To SDK with Bitstream

If there are errors for placement and routing, try to set environment variable XIL_PAR_ENABLE_LEGALIZER to 1, and rerun PAR.

Here’s my XPS Synthesis Summary (estimated).

XPS Synthesis Summary

Here’s partial ISE Device Utilization Summary.

ISE Device Utilization Summary

Follow PetaLinux SDK Board Bringup Guide to configure software settings of the hardware project and fs-boot.

I am using the following XMD commands to configure FPGA and download Linux image.

This is the PetaLinux login screen.

PetaLinux Login Screen

And PetaLinux Process Status.

PetaLinux Process Status

Another fun experiment is to write code to turn on and off LEDs in certain patterns. 4 bit LED IP’s address is 0×40000000, to turn on all LEDs, you can use:

poke 0×40000000 0x0f

Let me know if you’re interested running my design, I have it here. If you like to try the commercial PetaLinux, please contact Petalogix.

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45 Responses to “Run Linux on Avnet Spartan-6 LX9 MicroBoard”

  1. servet ayok Says:

    Hello Mr CAO,
    I would like to use microblaze and linux to interface a system using TCP/IP. Specifically, my system needs to give dynamic IP to the device connected to it, I mean it should act as a DHCP server.
    Is your design suitable for this, can I directly use your bit file for my lx9 microboard?
    You said “If you like to try the commercial PetaLinux, please contact Petalogix.” is the commercial version free? what is the difference between commercial version and the one you used?
    I would appriciate if you can help me.
    Thanks for your help.

    • tingcao Says:

      When I did the design (just for LX9 MicroBoard), I used static IP address.
      I’m sure you can enable DHCP server, either during kernel config, or add that functionality as a custom app.
      I will check that out when I have time.

      You’re welcome to use my bit file.

      If you want to build your own custom Linux kernel for Spartan-6 device MicroBlaze, you have two options:
      1) Use free distribution:
      Michal Simek


      2) Use the commercial Petalinux, which is not cheap, but will get you to the market sooner.
      This is what I’m using, but will try 1) later.

  2. servet ayok Says:

    Hello Mr CAO,
    Firstly I wanna thank you for your help. I used your .bit and .elf files and started linux on my microboard. But when I restart my board, I think I need to reload the image. I can convert bit file to mcs file and load it to flash so, FPGA can boot with microblaze. Is there a way that when FPGA boots, microblaze starts with Linux and I dont have to download linux again?
    Waiting to hear from you,

    • tingcao Says:

      Actually that’s what I’m going to do:
      1) program SPI flash, so the board is configured when powered on.
      2) add more peripherals, like DIP? Hope there is still resource left.
      3) add more apps, to drive LEDs? Hope I can time to do it.

      So expecting another post or two in coming weeks.

  3. servet ayok Says:

    When we program SPI flash, board will be configured with just microblaze not linux, we will have to download linux again. Am I true?
    Is not there a way to boot with microblaze and linux together so it is a stand alone module?

  4. Configure FPGA/SPI Flash to Run Linux on LX9 MicroBoard, Part 1 – Preparation « Ting Cao's Blog Says:

    [...] The FPGA design is done with ISE 13.2 based on AXI/Little Endian MicroBlaze 8.20a. The details were presented here at Run Linux on Avnet Spartan-6 LX9 MicroBoard. [...]

  5. Sven Andersson Says:

    I have followed your instructions and generated the hardware design. My axi.4_0_wrapper is almost twice as big as yours (562f/f 375 LUTs). Did you change the configuration of the AXI4 wrapper?


    • tingcao Says:

      Hi Sven, I didn’t change AXI configuration, and not sure why your AXI4 wrapper takes more resources.
      I believe AXI4 is only used by external memory LPDDR.

      I did change how to use AXI4 Lite for peripherals. In my design, I removed MDM’s AXI4 Lite connection (JTAG/UART). That’s one of the two keys to fit the design into LX9 device.
      Here’s my MHS if you’re interested.

      By the way, I read all (almost, :-) ) of your blogs, way back several years ago. I’m still enjoying to read them. Great work indeed.


    • Sven Andersson Says:

      Thanks for sending me the mhs file. I was using two different clocks (66MHz and 100MHz) in my system which added a lot of logic.


  6. fpga Says:

    Any change to not use petalinux but the following : ???

  7. Magali Says:

    Good article. Its realy nice. More information help me.

  8. Mostofa Noor Says:


  9. cianuro Says:


    I’m trying to make this work without Petalinux and I’m facing a few problems. I think that I’m having some kind of trouble configuring the Linux kernel. Could you post your .config file along the sources of the XPS project? That’d be great!

    Thank you!

  10. Kursad Gol Says:

    Hi Mr. CAO,

    Clearly i wanna ask you a pretty question? Please can you provide me your custom petalinux vhdl and c codes for educational using? Thanks in advance.

    Best regards.

  11. Kursad Gol Says:

    Hi Mr. CAO,

    I started to develop my project and i will feed you about my experiences back. But from now on there is a different problem from C codes issue. Daily problem is; i set environment variable XIL_PAR_ENABLE_LEGALIZER to 1 but anything changes about 3 ERRORS:

    ERROR:Place:543 – This design does not fit into the number of slices available in this device due to the complexity of
    the design and/or constraints.

    ERROR:Place:120 – There were not enough sites to place all selected components.

    Total REAL time to Placer completion: 3 hrs 42 mins 59 secs
    Total CPU time to Placer completion: 3 hrs 42 mins 48 secs
    ERROR:Pack:1654 – The timing-driven placement phase encountered an error.

    Is there any knowledge regarding this issue?

    Thank you again very much.

    • Kursad Gol Says:

      And i forgot and also my PC uses Windows XP Pro service pack 3. My design suite is ISE 13.2. I try to configure and program my board using iMPACT with the on-board USB-JTAG circuitry.

    • tingcao Says:

      I would suggest review your design, to drop any IPs not actually needed. Use only one clock source, check Sven Andersson’s comment on 2011/10/20.
      Make sure XIL_PAR_ENABLE_LEGALIZER kicks in. If you set it up from a console, start EDK from that same console.

      • Kursad Gol Says:

        Hi Mr. CAO,

        I solve the mapping anp placement prolem. But still i have a problem too. When I do “Export hardware design to SDK with bitstream” and after this i did “Program FPGA” on SDK v13.2 I have my_project.bit files 333 KB and microblaze_0.elf 1KB. I am sure i couldn’t create the right download.bit file. Because these files are dummy files. What will be the problem?

        Thank you very much indeed.

  12. Kursad Gol Says:

    And also i have too many warnings on my generation bit file. ISE v13.2 Design Summary says that “No errors and 284 warnings” Is this can be the problem? My computer’s Operating System is Windows XP Pro 2002 with Service Pack 3.

  13. Kursad Gol Says:

    With your experience, what am i doing wrong?

    • Kursad Gol Says:

      Could you please explain with snapshots the musts of creating bit file? Because your sopc_lx9.mcs file is running and its capacity is 30 MByte? But mine is 333 KByte?

      • tingcao Says:

        The actual size is about 1/3 of that of mcs (in ascii encoding).
        I have bootloader, Linux kernel and Linux apps built in, that’s why it is about 11M.

      • Kursad Gol Says:

        Hi Mr. CAO,

        Can the problem ocuured because of my computer’s operating system Windows XP? At your petalinux project given as .mcs file write “Linux version (tcao@ubuntu) (gcc version 4.1.2) #8 Tue Oct 11 00:46:35 MDT 2011″.

        Thank you.

      • tingcao Says:

        On which OS (XP, Linux, etc) you run the design tool (ISE/EDK) does no matter. Make sure you include the bit stream, and you app (such as Linux), etc.

  14. Tom Rae Says:

    Mr. Cao,

    Are the pmod connectors wired up on your LX9 Petalinux build?
    If so, how?

    Thank You,

    • tingcao Says:

      Hi Tom, I didn’t use pmod peripherals in my Petalinux build.
      I have a camera board which takes 2 pmod connectors, will try it once I get a chance. Since the space is tight on LX9, I probably will do a camera pmod design, and with Xilinx kernel but not with Linux support.

  15. vysakhpillai Says:

    Reblogged this on EmbeddedInn.

  16. MagicPhoton Says:

    Hi Cao,

    I know that you posted this blog a long time ago but i will be very grateful if you could try to help me.

    I’m using ISE 13.2 on windows XP and BXD 13.2 for Avnet LX9 microboard. I followed all yours steps until the Synthesis. I removed MDM’s AXI4 Lite connection (JTAG/UART). I am using only 66 MHz clock but I don’t know why my number of Slice LUTs is at 102% when in your design is amazingly at 84%.

    I check your MHS file and i find a little differences I tried too to do the synthesis with your file and I had the same result. Any suggestion?

    I couldn’t find XIL_PAR_ENABLE_LEGALIZER variable, in what file is placed? What you means with rerun PAR?

    Congratulations for this blog and thank you very much for share your knowledge. Thanks in advance and best regards.


  17. Sven Andersson Says:

    Hi MagicPhoton,

    I noticed the same thing when I moved from ISE 13.1 to ISE 13.2.
    I think the reason is that Xilinx has updated some of its IP blocks which made the larger. I never manage to fit the design into the FPGA anymore.


  18. Salman Sheikh Says:


    I am getting errors when setting the cache addresses like yours…these addresses seem to cover more than 8KB from 0×80000000 to 0x83ffffff?

    ERROR:EDK:3900 – issued from TCL procedure “check_cache” line 44
    microblaze_0 (microblaze) – Cacheable segment size defined by C_DCACHE_BASEADDR = 0×08000000 and C_DCACHE_HIGHADDR = 0x83FFFFFF must be a power-of-two.

    ERROR:EDK:3900 – issued from TCL procedure “check_cache” line 44
    microblaze_0 (microblaze) – Cacheable segment size defined by C_DCACHE_BASEADDR = 0×08000000 and C_DCACHE_HIGHADDR = 0x83FFFFFF must be a power-of-two.

    ERROR:EDK:3900 – issued from TCL procedure “check_cache” line 44
    microblaze_0 (microblaze) – Cacheable segment size defined by C_DCACHE_BASEADDR = 0×08000000 and C_DCACHE_HIGHADDR = 0x83FFFFFF must be a power-of-two.

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